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? semiconductor components industries, llc, 2011 march, 2017 ? rev. 14 1 publication order number: ar0331/d ar0331 ar0331 1/3\inch 3.1 mp/full hd digital image sensor general description the on semiconductor ar0331 is a 1/3-inch cmos digital image sensor with an active-pixel array of 2048 (h) x 1536 (v). it captures images in either linear or high dynamic range modes, with a rolling-shutter readout. it includes sophisticated camera functions such as in-pixel binning, windowing and both video and single frame modes. it is designed for both low light and high dynamic range scene performance. it is programmable through a simple two-wire serial interface. the ar0331 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and hd video. the on semiconductor ar0331 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. the default mode output is a 1080p-resolution image at 60 frames per second (fps). in linear mode, it outputs 12-bit or 10-bit a-law compressed raw data, using either the parallel or serial (hispi) output ports. in high dynamic range mode, it outputs 12-bit compressed data using parallel output. in hispi mode, 12- or 14-bit compressed, or 16-bit linearized data may be output. the device may be operated in video (master) mode or in single frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. the ar0331 includes additional features to allow application- specific tuning: windowing and offset, auto black level correction, and on-board temperature sensor. optional register information and histogram statistic information can be embedded in the first and last 2 lines of the image frame. the sensor is designed to operate in a wide temperature range (?30 c to +85 c). features ? superior low-light performance ? latest 2.2 m pixel with on semiconductor a-pix ? technology ? full hd support at 1080 p 60 fps for superior video performance ? linear or high dynamic range capture ? 3.1 m (4:3) and 1080 p full hd (16:9) images ? optional adaptive local tone mapping (altm) ? interleaved t1/t2 output ? support for external mechanical shutter ? support for external led or xenon flash ? slow-motion video (vga 120 fps) ? on-chip phase-locked loop (pll) oscillator ? integrated position-based color and lens shading correction ? slave mode for precise frame-rate control ? stereo/3d camera support ? statistics engine www. onsemi.com see detailed ordering and shipping information on page 2 of this data sheet. ordering information ilcc48 10x10 case 847ag ? data interfaces: four-lane serial high-speed pixel interface (hispi) differential signaling (slvs and hiv cm ), or parallel ? auto black level calibration ? high-speed context switching ? temperature sensor applications ? video surveillance ? stereo vision ? smart vision ? automation ? machine vision ? 1080p60 video applications ? high dynamic range imaging ibga52 9x9 case 503aa
ar0331 www. onsemi.com 2 table 1. key parameters parameter typical value optical format 1/3-inch (5.8 mm) note: sensor optical format will also work with lenses designed for 1/3.2? format. active pixels 2048 (h) x 1536 (v) (4:3, mode) pixel size 2.2 m x 2.2 m color filter array rgb bayer shutter type electronic rolling shutter and grr input clock range 6 ? 48 mhz output clock maximum 148.5 mp/s (4-lane hispi) 74.25 mp/s (parallel) output serial hispi 10-, 12-, 14-, or 16-bit parallel 10-, 12-bit frame rate full resolution 30 fps 1080p 60 fps responsivity 1.9 v/lux-sec snr max 39 db max dynamic range up to 100 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v hispi 0.3 v ? 0.6 v, 1.7 v ? 1.9 v power consumption (typical) <780 mw operating temperature (ambient) ?30 c to +85 c package options 10 x 10 mm 48 pin ilcc 9.5 x 9.5 mm 63-pin ibga ordering information table 2. available part numbers part number product description orderable product attribute description ar0331srsc00shca0-drbr 48-pin ilcc hispi, 0 cra dry pack without protective film, double side bbar glass ar0331srsc00shcad3-gevk 48-pin ilcc hispi, 0 cra demo kit 3 AR0331SRSC00SHCAD-GEVK 48-pin ilcc hispi, 0 cra demo kit ar0331srsc00shcah-gevb 48-pin ilcc hispi, 0 cra demo board ar0331srsc00suca0-dpbr 48-pin ilcc parallel, 0 cra dry pack with protective film, double side bbar glass ar0331srsc00suca0-drbr 48-pin ilcc parallel, 0 cra dry pack without protective film, double side bbar glass ar0331srsc00sucad3-gevk 48-pin ilcc parallel, 0 cra demo kit 3 ar0331srsc00sucad-gevk 48-pin ilcc parallel, 0 cra demo kit ar0331srsc00sucah-gevb 48-pin ilcc parallel, 0 cra demo board ar0331srsc00xuead3-gevk 63-pin ibga demo kit 3 ar0331srsc00xuead-gevk 63-pin ibga demo kit ar0331srsc00xueah-gevb 63-pin ibga demo board ar0331srsc00xuee0 ? by ? drbr 63-pin ibga, 0 cra dry pack without protective film, double side bbar glass ar0331srsc00xuee0-dpbr 63-pin ibga, 0 cra dry pack with protective film, double side bbar glass ar0331srsc00xuee0-drbr 63-pin ibga, 0 cra dry pack without protective film, double side bbar glass ar0331srsc00xuee0-drbr1 63-pin ibga, 0 cra dry pack without protective film, double side bbar glass
ar0331 www. onsemi.com 3 functional overview the ar0331 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phase-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 mhz. the maximum output pixel rate is 148.5 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diagram of the sensor. figure 1. block diagram row noise correction black level correction adaptive cd filter motion correction and blue halo filter hdr linearization (me or dlo) pixel defect correction smooting filter digital gain and pedestal 12 12 16 companding 16, 14, or 12 bits parallel hispi 12 bits ( hdr and linear), 12 or 10 bits linear test pattern generator adc data user interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. the core of the sensor is a 3.1 mp active-pixel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog-to-digital converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). the sensor also offers a high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 16-bit per pixel value. a compression mode is further offered to allow the 16-bit pixel value to be transmitted to the host system as a 12-bit value with close to zero loss in image quality.
ar0331 www. onsemi.com 4 figure 2. typical configuration: serial four-lane hispi interface vaa_pix master clock (6?48 mhz) d gnd digital ground analog ground 1.5 kw 2 1.5 kw 2 notes: 1. all power supplies should be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 3. the parallel interface output pads can be left unconnected if the serial output interface is used. 4. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on layout and design considerations. refer to the ar0331 demo headboard schematics for circuit recommendations. 5. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match vdd_io voltage to minimize any leakage currents. extclk from controller v dd _io v dd v dd _slvs v dd _pll v aa to controller digital i/0 power 1 digital core power 1 hispi power 1 pll power 1 analog power 1 analog power 1 v dd _io v dd v dd _slvs v dd _pll v aa a gnd slvsc_n slvsc_p slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n slvs3_p slvs3_n shutter flash s data sclk reset_bar test trigger oe_bar s addr v aa _pix
ar0331 www. onsemi.com 5 figure 3. typical configuration: parallel pixel data interface notes: master clock (6?48 mhz) s data sclk reset_bar test flash frame_valid shutter d out [11:0] extclk d gnd digital ground analog ground to controller line_valid pixclk 1.5k 2 1.5k 2 vaa_pix v dd _io v dd v dd _pll v aa v dd _io v dd v dd _pll v aa digital i/0 power 1 digital core power 1 pll power 1 analog power 1 analog power 1 1. all power supplies should be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 3. the serial interface output pads and v dd slvs can be left unconnected if the parallel output interface is used. 4. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on layout and design considerations. refer to the ar0331 demo headboard schematics for circuit recommendations. 5. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. 7. the extclk input is limited to 6 ? 48 mhz. s addr oe_bar trigger a gnd from controller v aa _pix
ar0331 www. onsemi.com 6 figure 4. 48 ilcc package, parallel output d out 7 d out 8 d out 9 d out 10 d out 11 v dd _io pixclk v dd s clk s data reset_bar v dd _io nc nc v aa a gnd v aa _pix reserved nc v aa _pix v aa a gnd v aa reserved v dd nc nc nc oe_bar s addr test flash trigger frame_valid line_valid d gnd extclk v dd _pll d out 6 d gnd d gnd d out 5 d out 4 d out 3 d out 2 d out 1 d out 0 nc 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 19 20 21 22 23 24 25 26 27 28 29 30 6 5 4 3 2 1 48 47 46 45 44 43 table 3. pin description pin number name type description 1 d out 4 output parallel pixel data output 2 d out 5 output parallel pixel data output 3 d out 6 output parallel pixel data output 4 v dd _pll power pll power 5 extclk input external input clock 6 d gnd power digital ground 7 d out 7 output parallel pixel data output 8 d out 8 output parallel pixel data output 9 d out 9 output parallel pixel data output 10 d out 10 output parallel pixel data output
ar0331 www. onsemi.com 7 table 3. pin description (continued) pin number description type name 11 d out 11 output parallel pixel data output (msb) 12 v dd_ io power i/o supply power 13 pixclk output pixel clock out. d out is valid on rising edge of this clock 14 v dd power digital power 15 s clk input two-wire serial clock input 16 s data i/o two-wire serial data i/o 17 reset _ bar input asynchronous reset (active low). all settings are restored to factory default 18 v dd_ io power i/o supply power 19 v dd power digital power 20 nc 21 nc 22 nc 23 oe_bar input output enable (active low) 24 s addr input two-wire serial address select. 0: 0x20. 1: 0x30 25 test input manufacturing test enable pin (connect to d gnd ) 26 flash output flash output control 27 trigger input receives slave mode vd signal for frame rate synchronization and trigger to start a grr frame 28 frame_valid output asserted when d out frame data is valid 29 line_valid output asserted when d out line data is valid. 30 d gnd power digital ground 31 reserved 32 shutter output control for external mechanical shutter. can be left floating if not used 33 reserved 34 v aa power analog power 35 a gnd power analog ground 36 v aa power analog power 37 v aa_ pix power pixel power 38 v aa_ pix power pixel power 39 a gnd power analog ground 40 v aa power analog power 41 nc 42 nc 43 nc 44 d gnd power digital ground 45 d out 0 output parallel pixel data output (lsb) 46 d out 1 output parallel pixel data output 47 d out 2 output parallel pixel data output 48 d out 3 output parallel pixel data output
ar0331 www. onsemi.com 8 figure 5. 48 ilcc package, hispi output d gnd v dd _io s clk s data reset_bar nc v aa v aa _pix reserved v aa _pix v aa a gnd v dd nc oe_bar flash trigger v dd _pll slvs0_n slvs1_n d gnd nc 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 19 20 21 22 23 24 25 26 27 28 29 30 6 5 4 3 2 1 48 47 46 45 44 43 slvs0_p slvs1_p slvsc_n slvsc_p slvs2_n slvs2_p slvs3_n slvs3_p d gnd v dd _io s addr nc d gnd reserved test v dd extclk v dd d gnd v dd _io v dd _slvs a gnd nc v aa nc shutter table 4. pin description, 48 ilcc pin number name type description 1 slvsc_n output hispi serial ddr clock differential n 2 slvs1_p output hispi serial data, lane 1, differential p 3 slvs1_n output hispi serial data, lane 1, differential n 4 slvs0_p output hispi serial data, lane 0, differential p 5 slvs0_n output hispi serial data, lane 0, differential n 6 nc 7 v dd _slvs power 0.3 v ? 0.6 v or 1.7 v ? 1.9 v port to hispi output driver. set the high_vcm (r0x306e[9]) bit to 1 when configuring v dd _slvs to 1.7?1.9 v 8 v dd _io power i/o supply power 9 d gnd power digital ground 10 v dd power digital power
ar0331 www. onsemi.com 9 table 4. pin description, 48 ilcc (continued) pin number description type name 11 extclk input external input clock 12 v dd power digital power 13 d gnd digital ground 14 v dd_ io power i/o supply power 15 s data i/o two-wire serial data i/o 16 s clk input two-wire serial clock input 17 test manufacturing test enable pin (connect to d gnd ) 18 reset _ bar input asynchronous reset (active low). all settings are restored to factory default 19 v dd power digital power 20 d gnd power digital ground 21 v dd_ io power i/o supply power 22 nc 23 s addr input two-wire serial address select. 0: 0x20. 1: 0x30 24 nc 25 oe_bar output enable (active low) 26 trigger input receives slave mode vd signal for frame rate synchronization and trigger to start a grr frame 27 flash output flash output control 28 d gnd power 29 v dd _pll power pll power 30 reserved 31 a gnd power analog ground 32 v aa power analog power 33 reserved 34 shutter output control for external mechanical shutter. can be left floating if not used 35 v aa_ pix power pixel power 36 v aa_ pix power pixel power 37 nc 38 v aa power analog power 39 nc 40 nc 41 v aa power analog power 42 a gnd power analog ground 43 d gnd power digital ground 44 slvs3_p output hispi serial data, lane 3, differential p 45 slvs3_n output hispi serial data, lane 3, differential n 46 slvs2_p output hispi serial data, lane 2, differential p 47 slvs2_n output hispi serial data, lane 2, differential n 48 slvsc_p output hispi serial ddr clock differential p
ar0331 www. onsemi.com 10 figure 6. 9.5 x 9.5 mm 63 ? ball ibga package a b c d e f g h top view (ball down) slvs0_n slvs0_p slvs1_n slvs1_p v dd nc v dd _pll slvs_cn slvsc_p slvs2_n slvs2_p v dd v aa v aa extclk v dd _ slvs slvs3_n slvs3_p d gnd v dd a gnd s addr s clk s data d gnd d gnd v dd v aa _pix v aa _pix line_ valid frame_ valid pixclk flash d gnd v dd _io nc d out 8 d out 9d out 10 d out 11 d gnd v dd _io test d out 4d out 5d out 6d out 7d gnd v dd _io trigger oe_bar d out 0d out 1d out 2d out 3d gnd v dd _io v dd _io reset_ bar 12 3 567 8 4 v dd a gnd shutter reserved (nc) table 5. pin descriptions, 9.5 x 9.5 mm, 63-ball ibga name ibga pin type description slvs0_n a2 output hispi serial data, lane 0, differential n slvs0_p a3 output hispi serial data, lane 0, differential p slvs1_n a4 output hispi serial data, lane 1, differential n slvs1_p a5 output hispi serial data, lane 1, differential p v dd _pll b1 power pll power. slvsc_n b2 output hispi serial ddr clock differential n slvsc_p b3 output hispi serial ddr clock differential p slvs2_n b4 output hispi serial data, lane 2, differential n slvs 2_ p b5 output hispi serial data, lane 2, differential p v aa b7, b8 power analog power extclk c1 input external input clock. v dd_ slvs c2 power 0.3 v ? 0.6 v or 1.7 v ? 1.9 v port to hispi output driver. set the high_vcm (r0x306e[9]) bit to 1 when configuring vdd_slvs to 1.7?1.9 v slvs3_n c3 output hispi serial data, lane 3, differential n slvs3_p c4 output hispi serial data, lane 3, differential p d gnd c5, d4, d5, e5, f5, g5, h5 power digital ground
ar0331 www. onsemi.com 11 table 5. pin descriptions, 9.5 x 9.5 mm, 63-ball ibga (continued) name description type ibga pin v dd a6, a7, b6, c6, d6 power digital power a gnd c7, c8 power analog ground s addr d1 input two-wire serial address select. 0: 0x20. 1: 0x30 s clk d2 input two-wire serial clock input s data d3 i/o two-wire serial data i/o v aa _pix d7, d8 power pixel power line_valid e1 output asserted when d out line data is valid frame_valid e2 output asserted when d out frame data is valid. pixclk e3 output pixel clock out. d out is valid on rising edge of this clock. v dd _io e6, f6, g6, h6, h7 power i/o supply power d out 8 f1 output parallel pixel data output d out 9 f2 output parallel pixel data output d out 10 f3 output parallel pixel data output d out 11 f4 output parallel pixel data output (msb) test f7 input. manufacturing test enable pin (connect to d gnd ) d out 4 g1 output parallel pixel data output d out 5 g2 output parallel pixel data output d out 6 g3 output parallel pixel data output d out 7 g4 output parallel pixel data output trigger g7 input exposure synchronization input oe_bar g8 input output enable (active low) d out 0 h1 output parallel pixel data output (lsb) d out 1 h2 output parallel pixel data output d out 2 h3 output parallel pixel data output d out 3 h4 output parallel pixel data output reset_bar h8 input asynchronous reset (active low). all settings are restored to factory default shutter e8 output control for external mechanical shutter. can be left floating if not used flash e4 output flash control output nc a8, e7 reserved f8
ar0331 www. onsemi.com 12 pixel data format pixel array structure while the sensor?s format is 2048 x 1536, additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. the pixel adjustment is always performed for monochrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. not all dummy pixels or barrier pixels can be read out. figure 7. pixel array description 16 barrier + 4 border pixels light dummy active pixel pixel 2064 18 barrier + 4 border pixels 2 barrier + 4 border pixels 1578 2 barrier + 4 border pixels 2052 1 x 1536 4.51mm x 3.38 mm 1. maximum of 2048 columns is supported. additional columns included for mirroring operations. figure 8. pixel color pattern detail (top right corner) active pixel (0,0) array pixel (0, 0) rowreado ut direction g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction
ar0331 www. onsemi.com 13 default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 8 ). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in default condition is that of pixel (0, 0). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 9. when the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in figure 9. figure 9. imaging a scene lens pixel (0,0) row readout order column readout order scene sensor (rear view)
ar0331 www. onsemi.com 14 pixel output interfaces parallel interface the parallel pixel data interface uses these output-only signals: ? frame_valid ? line_valid ? pixclk ? d out [11:0] the parallel pixel data interface is disabled by default at power up and after reset. it can be enabled by programming r0x301a. table 7 shows the recommended settings. when the parallel pixel data interface is in use, the serial data output signals can be left unconnected. set reset_register [bit 12 (r0x301a[12] = 1)] to disable the serializer while in parallel output mode. output enable control when the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and high-z under pin or register control, as shown in table 6. table 6. output enable control oe_bar pin drive pins r0x301a[6] description 1 0 interface high-z x 1 interface driven 0 x interface driven configuration of the pixel data interface fields in r0x301a are used to configure the operation of the pixel data interface. the supported combinations are shown in table 7. table 7. configuration of the pixel data interface serializer disable r0x301 a[12] parallel enable r0x301 a[7] description 0 0 power up default serial pixel data interface and its clocks are enabled. transitions to soft standby are synchronized to the end of frames on the serial pixel data interface 1 1 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface high speed serial pixel data interface the high speed serial pixel (hispi) interface uses four data lanes and one clock as output. ? slvsc_p ? slvsc_n ? slvs0_p ? slvs0_n ? slvs1_p ? slvs1_n ? slvs2_p ? slvs2_n ? slvs3_p ? slvs3_n the hispi interface supports three protocols, streaming-s, streaming-sp, and packetized sp. the streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. the packetized sp protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. these protocols are further described in the high-speed serial pixel (hispi) interface protocol specification v1.50.00. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. figure 10 shows the configuration between the hispi transmitter and the receiver. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. figure 10 shows the configuration between the hispi transmitter and the receiver.
ar0331 www. onsemi.com 15 figure 10. hispi transmitter and receiver interface block diagram a camera containing the hispi transmitter a host (dsp) containing the hispi receiver dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0 tx phy0 rx phy0 dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0 hispi physical layer the hispi physical layer is partitioned into blocks of four data lanes and an associated clock lane. any reference to the phy in the remainder of this document is referring to this minimum building block. the phy will serialize 10-, 12-, 14-, or 16-bit data words and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of the clock. figure 11 shows bit transmission. in this example, the word is transmitted in order of msb to lsb. the receiver latches data at the rising and falling edge of the clock. figure 11. timing diagram cp dn msb lsb txpost dp cn 1 ui txpre dll timing adjustment the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in pcb design. delay compensation may be set for clock and/or data lines in the hispi_timing register r0x31c0. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. figure 12. block diagram of dll timing adjustment delay delay del 1[2: 0] delay delay del 3[2: 0] delay del 2[2: 0] data _lane 0 data _lane 1 clock_lane0 delclock[2:0] data_lane2 data_lane3 data0_del[2:0]
ar0331 www. onsemi.com 16 figure 13. delaying the clock with respect to data 1 ui cp (clock_del = 000) datan (datan_del = 000) cp (clock_del = 001) cp (clock_del = 010) cp (clock_del = 011) cp (clock_del = 100) cp (clock_del = 101) cp (clock_del = 110) cp (clock_del = 111) increasing clock_del[2:0] increases clock delay figure 14. delaying data with respect to the clock 1 ui t dllstep cp (clock_del = 000) datan (datan_del = 000) datan (datan_del = 001) datan (datan_del = 010) datan (datan_del = 011) datan (datan_del = 100) datan (datan_del = 101) datan (datan_del = 110) datan (datan_del = 111) increasing datan_del[2:0] increases data delay hispi protocol layer the hispi protocol is described the hispi protocol specification document. serial configuration the serial format should be configured using r0x31ac. refer to the ar0331 register reference document for more detail regarding this register. the serial_format register (r0x31ae) controls which serial format is in use when the serial interface is enabled (reset_register[12] = 0). the following serial formats are supported: ? 0x0304 ? sensor supports quad-lane hispi operation ? 0x0302 ? sensor supports dual-lane hispi operation ? 0x0301 ? sensor supports single-lane hispi operation
ar0331 www. onsemi.com 17 pixel sensitivity figure 15. integration control in ers readout row reset (start of integration) row readout row integration (t integration ) a pixel?s integration time is defined by the number of clock periods between a row?s reset and read operation. both the read followed by the reset operations occur within a row period (t row ) where the read and reset may be applied to different rows. the read and reset operations will be applied to the rows of the pixel array in a consecutive order. the coarse integration time is defined by the number of row periods (t row ) between a row?s reset and the row read. the row period is defined as the time between row read operations (see sensor frame rate). t coarse t row coarse_integration_time (eq. 1) figure 16. example of 8.33 ms integration in 16.6 ms frame vertical blanking read reset vertical blanking horizontal blanking t coarse = coarse_integration_time x t row 8.33 ms = 563 rows x 22.2 s/row t frame = frame_length_lines x t row 16.6 ms = 750 rows x 22.22 s/row
ar0331 www. onsemi.com 18 figure 17. the row integration time is greater than the frame readout time vertical blanking read shutter vertical blanking horizontal blanking t coarse = coarse_integration_time x t row t frame = frame_length_lines x t row 20.7 ms = 1390 rows x 14.8 s/row 16.6 ms = 1125rows x 14.8 s/row horizontal blanking image image 4.1 ms pointer pointer time extended vertical blanking the minimum frame-time is defined by the number of row periods per frame and the row period. the sensor frame-time will increase if the coarse_integration_time is set to a value equal to or greater than the frame_length_lines. gain stages the analog gain stages of the ar0331 sensor are shown in figure 18. the sensor analog gain stage consists of a variable adc reference. the sensor will apply the same analog gain to each color channel. digital gain can be configured to separate levels for each color channel. figure 18. gain stages in ar0331 sensor adc reference digital gain with dithering 1x, 2x, 4x, and 8x 1x to 16x (128 steps per 6db) the level of analog gain applied is controlled by the coarse_gain register. the recommended analog gain settings are listed in table 8. a minimum analog gain of 1.23x is recommended. changes to these registers should be done prior to streaming images.
ar0331 www. onsemi.com 19 table 8. recommended sensor gain coarse_gain(0x3060[5:4])/ coarse_gain_cb (0x3060[13:12]) fine_gain (0x3060[3:0])/ fine_gain_cb (0x3060[11:8]) adc gain 0 6 1.23 0 7 1.28 0 8 1.34 0 9 1.39 0 10 1.45 0 11 1.52 0 12 1.60 0 13 1.69 0 14 1.78 0 15 1.88 1 0 2.00 1 2 2.14 1 4 2.28 1 6 2.47 1 8 2.67 1 10 2.91 1 12 3.20 1 14 3.56 2 0 4 2 4 4.56 2 8 5.34 2 12 6.41 3 0 8 each digital gain can be configured from a gain of 0 to 15.992. the digital gain supports 128 gain steps per 6db of gain. the format of each digital gain register is ?xxxx.yyyyyyy? where ?xxxx? refers an integer gain of 1 to 15 and ?yyyyyyy? is a fractional gain ranging from 0/128 to 127/128. the sensor includes a digital dithering feature to reduce quantization noise resulting from using digital gain. it can be disabled by setting r0x30ba[5] to 0. the default value is 1. pedestals there are two types of constant offset pedestals that may be adjusted at the end of the datapath. the data pedestal is a constant offset that is added to pixel values at the end of the datapath. the default offset when altm is disabled is 168 and is a 12-bit offset. this offset matches the maximum range used by the corrections in the digital readout path. the purpose of the data pedestal is to convert negative values generated by the digital datapath into positive output data. it is recommended that the data pedestal be set to 16 when altm is enabled. the data pedestal value can be changed from its default value by adjusting register r0x301e. the altm pedestal (r0x2450) is also located at the end of the datapath. the altm pedestal default offset is 0.
ar0331 www. onsemi.com 20 high dynamic range mode by default, the sensor powers up in hdr mode. the hdr scheme used is multi-exposure hdr. this allows the sensor to handle up to 100 db of dynamic range. in hdr mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the rolling shutter readout. the intermediate pixel values are stored in line buffers while waiting for the two exposure values to be present. as soon as a pixel?s two exposure values are available, they are combined to create a linearized 16-bit value for each pixel?s response. depending on whether hispi or parallel mode is selected, the full 16 bit value may be output, it can be compressed to 12 bits using adaptive local tone mapping (altm), or companded to 12 or 14 bits. adaptive local tone mapping real- world scenes often have a very high dynamic range (hdr) that far exceeds the electrical dynamic range of the imager. dynamic range is defined as the luminance ratio between the brightest and the darkest objects in a scene. even though the ar0331 can capture full dynamic range images, the images are still limited by the low dynamic range of display devices. today?s typical lcd monitor has a contrast ratio around 1000:1 while it is not atypical for an hdr image having a contrast ratio of around 250000:1. therefore, in order to reproduce hdr images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. this is commonly called tone mapping. the ar0331 has implemented an adaptive local tone mapping (altm) feature to reproduce visually appealing images that increase the local contrast and the visibility of the images. when altm is enabled, the gamma in the backend isp should be set to 1 for proper display. see the ar0331 developer guide for more information on altm. companding the 16-bit linearized hdr image may be compressed to 12 bits using on-chip companding. figure 19 illustrates the compression from 16- to 12-bits. companding is enabled by setting r0x31d0. table 10 shows the knee points for the different modes. figure 19. hdr data compression 500 1000 1500 2000 2500 3000 3500 4000 4500 0 10000 20000 30000 40000 50000 60000 70000 0 12-bit code output 16-bit code input
ar0331 www. onsemi.com 21 table 9. companding table segment 1 segment 2 segment 3 segment 4 input code range 0 to 1023 1024 to 4095 4096 to 32767 32768 to 65535 output code range 0 to 1023 1024 to 2559 2560 to 3455 3456 to 3967 companding formula p out = p in p out = (p in ? 1024)/2 + 1024 p out = (p in ? 4096)/32 + 2560 p out = (p in ? 32768)/64 + 3456 decompanding formula p out = p in p out = (p in ? 1024)*2 + 1024 p out = (p in ? 2560)*32 + 4096 p out = (p in ? 3456)*64 + 32768 table 9 illustrates the input and output codes as well as companding and decompanding formulas for each of the four colored segments in figure 19. table 10. knee points for compression from 16 bits to 12 bits t1/t2 exposure ratio (r1) r0x3082[3:2] p1 p out1 = p1 p2 p out 2= (p2 ? p1)/2 + 1024 p3 p out 3= (p3 ? p2)/32 + 2560 pmax p out max = (pmax ? p3)/64 + 3456 4x, 8x, 16x, 32x 2 10 1024 2 12 2560 2 15 3456 2 16 3968 as described in t able 10, the ar0331 companding block operates on 16-bit input only. for the exposure ratios that do not result in 16-bits, bit shifting occurs before the data enters the companding block. as a result of the bit shift, data needs to be unshifted after linearization in order to obtain the proper image. table 11 provides the bit operation that should occur to the data after linearization. table 11. bit operation after linearization ratio_t1_t2 (r0x3082[3:2])/ratio_t1_t2_cb (r0x3084[3:2]) bit shift operation after linearization 4x right shift 2 bits 8x right shift 1 bit 16x no shift 32x left shift 1 bit hdr-specific exposure settings in hdr mode, pixel values are stored in line buffers while waiting for both exposures to be available for final pixel data combination. there are 70 line buffers used to store intermediate t1 data. due to this limitation, the maximum coarse integration time possible for a given exposure ratio is equal to 70*t1/t2 lines. for example, if r0x3082[3:2] = 2, the sensor is set to have t1/t2 ratio = 16x. therefore the maximum number of integration lines is 70*16 = 1120 lines. if coarse integration time is greater than this, the t2 integration time will stay at 70. the sensor will calculate the ratio internally, enabling the linearization to be performed. if companding is being used, then relinearization would still follow the programmed ratio. for example if the t1/t2 ratio was programmed to 16x but coarse integration was increased beyond 1120 then one would still use the 16x relinearization formulas. an additional limitation is the maximum number of exposure lines in relation to the frame_length_lines register. in linear mode, maximum coarse_integration_time = frame_length_lines ? 1. however in hdr mode, since the coarse integration time register controls t1, the max coarse integration time is frame_length_lines ? 71. putting the two criteria listed above together, the formula is as follows: maximum coarse_integration_time minimum(70 t1 t2 , frame_length_lines?71) (eq. 2) there is a limitation of the minimum number of exposure lines, w hich is one row time for linear mode. in hdr mode, the minimum number of rows required is half of the ratio t1/t2.
ar0331 www. onsemi.com 22 motion compensation in typical multi-exposure hdr systems, motion artifacts can be created when objects move during the t1 or t2 integration time. when this happens, edge artifacts can potentially be visible and might look like a ghosting effect. to correct this, the ar0331 has special 2d motion compensation circuitry that detects motion artifacts and corrects the image. the motion compensation feature can be enabled by setting r0x318c[14] = 1. additional parameters are available to control the extent of motion detection and correction as per the requirements of the specific application. for more information, refer to the ar0331 register reference document and the ar0331 developer guide. reset the ar0331 may be reset by the reset_bar pin (active low) or the reset register. hard reset of logic the reset_bar pin can be connected to an external rc circuit for simplicity. the recommended rc circuit uses a 10 k resistor and a 0.1 f capacitor. the rise time for the rc circuit is 1 s maximum. soft reset of logic soft reset of logic is controlled by the r0x301a reset register. bit 0 is used to reset the digital logic of the sensor. furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. this bit is a self-resetting bit and also returns to ?0? during two-wire serial interface reads. sensor pll vco figure 20. pll dividers affecting vco frequency pre_pll_clk_div 2(1 ? 64) pll_multiplier 58(32 ? 384) f vc0 extclk (6 ? 48 mhz) the sensor contains a phase-locked loop (pll) that is used for timing generation and control. the required vco clock frequency is attained through the use of a pre-pll clock divider followed by a multiplier. the pll multiplier should be an even integer. if an odd integer (m) is programmed, the pll will default to the lower (m ? 1) value to maintain an even multiplier value. the multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. use of the pll is required when using the hispi interface.
ar0331 www. onsemi.com 23 dual readout paths there are two readout paths within the sensor digital block. the sensor pll should be configured such that the total pixel rate across both readout paths is equal to the output pixel rate. for example, if clk_pix is 74.25 mhz in a 4-lane hispi configuration, the clk_op should be equal to 37.125 mhz. figure 21. sensor dual readout paths clk_pix clk_pix pixel rate = 2 x clk_pix = # data lanes x clk_op (hispi) = clk_op (parallel) all digital blocks serial out- put (hispi) pixel array all digital blocks the sensor row timing calculation refers to each data-path individually. for example, the sensor default configuration uses 1100 clocks per row (line_length_pck) to output 1928 active pixels per row. the aggregate clocks per row seen by the receiver will be 2200 clocks (1100 x 2 readout paths). parallel pll configuration figure 22. pll for the parallel interface extclk (6 ? 48 mhz) clk_op (max 74.25 mp/s) clk_pix (max 37.125 mp/s) f vc0 pre_pll_clk_div 2(1 ? 64) pll_multiplier 58(32 ? 384) vt_sys_clk_div 1 (1,2,4,6,8,10 12,14,160 vt_pix_clk_div 6(4 ? 16) the maximum output of the parallel interface is 74.25 mpixel/s. this will limit the readout clock (clk_pix) to 37.125 mpixel/s. the sensor will not use the f serial , f serial_clk , or clk_op when configured to use the parallel interface. table 12. pll parameters for the parallel interface parameter symbol min max unit external clock extclk 6 48 mhz vco clock f vco 384 768 mhz readout clock clk_pix 37.125 mpixel/s output clock clk_op 74.25 mpixel/s
ar0331 www. onsemi.com 24 table 13. example pll configuration for the parallel interface parameter value output f vco 445.5 mhz (max) vt_sys_clk_div 1 vt_pix_clk_div 6 clk_pix 37.125 mpixel/s (= 445.5 mhz / 12) clk_op 74.25 mpixel/s (= 445.5 mhz / 6) output pixel rate 74.25 mpixel/s serial pll configuration figure 23. pll for the serial interface clk_pix clk_op pll_multiplier 58 (32 ? 384) pre_pll_clk_div 2 (1 ? 64) vt_sys_clk_div 1 (1, 2, 4, 6, 8, 10,11, 12,14, 16) vt_pix_clk_div 6 (4 ? 16) f vc0 f vc0 op_sys_clk_div (default = 1) op_pix_clk_div 12 (8,10, 12) f serial the pll must be enabled when hispi mode is selected. the sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per lane (clk_op). the configuration will depend on the number of active lanes (1, 2, or 4) configured. to configure the sensor protocol and number of lanes, refer to ?serial configuration?. table 14. pll parameters for the serial interface parameter symbol min max unit external clock extclk 6 48 mhz external clock extclk 6 48 mhz vco clock f vco 384 768 mhz readout clock clk_pix 74.25 mpixel/s output clock clk_op 37.125 mpixel/s output serial data rate per lane f serial 300 (hispi) 700 (hispi) mbps output serial clock speed per lane f serial_clk 150 (hispi) 350 (hispi) mhz
ar0331 www. onsemi.com 25 configure the serial output so that it adheres to the following rules: ? the maximum data-rate per lane (f serial ) is 700 mbps/lane (hispi). ? configure the output pixel rate per lane (clk_op) so that the sensor output pixel rate matches the peak pixel rate (2 x clk_pix). ? 4-lane: 4 x clk_op = 2 x clk_pix = pixel rate (max: 148.5 mpixel/s) ? 2-lane: 2 x clk_op = 2 x clk_pix = pixel rate (max: 74.25 mpixel/s) ? 1-lane: 1 x clk_op = 2 x clk_pix = pixel rate (max: 37.125 mpixel/s) table 15. example pll configurations for the serial interface parameter 4-lane 2-lane 1-lane units 16-bit 14-bit 12-bit 10-bit 12-bit 10-bit 10-bit f vco 594 519.75 445.5 742.5 445.5 742.5 742.5 mhz vt_sys_clk_div 1 1 1 2 1 2 4 vt_pix_clk_div 8 7 6 5 12 10 10 op_sys_clk_div 1 1 1 2 1 2 2 op_pix_clk_div 16 14 12 10 12 10 10 f serial 594 519.75 445.5 371.25 445.5 371.25 371.25 mhz f serial_clk 297 259.875 222.75 185.63 222.75 185.63 185.63 mhz clk_pix 74.25 74.25 74.25 74.25 37.125 37.125 18.563 mpixel/s clk_op 37.125 37.125 37.125 37.125 37.125 37.125 37.125 mpixel/s pixel rate 148.5 148.5 148.5 148.5 74.25 74.25 37.125 mpixel/s stream/standby control the sensor supports a soft standby mode. in this mode, the external clock can be optionally disabled to further minimize power consumption. if this is done, then the ?power-up sequence? must be followed. when the external clock is disabled, the sensor will be unresponsive to register writes and other operations. soft standby is a low-power state that is controlled through register r0x301a[2]. the sensor will go to standby after completion of the current frame readout. when the sensor comes back from soft standby, previously written register settings are still maintained. soft standby will not occur if the trigger pin is held high. a specific sequence needs to be followed to enter and exit from soft standby. entering soft standby: 1. set r0x301a[12] = 1 if serial mode was used 2. set r0x301a[2] = 0 and drive trigger pin low. 3. turn off external clock to further minimize power consumption exiting soft standby: 1. enable external clock if it was turned off 2. set r0x301a[2] = 1 or drive trigger pin high. 3. set r0x301a[12] = 0 if serial mode is used
ar0331 www. onsemi.com 26 sensor readout image acquisition modes the ar0331 supports two image acquisition modes: ? electronic rolling shutter (ers) mode: this is the normal mode of operation. when the ar0331 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when the ers is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. when the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the ar0331 switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?changes to integration time? in the ar0331 register reference. ? global reset mode: this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the ar0331 provides control signals to interface to that shutter. the benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ers operation. visual artifacts arise in ers operation, particularly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. window control the sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. readout modes horizontal mirror when the horiz_mirror bit (r0x3040[14]) is set in the read_mode register, the order of pixel readout within a row is reversed, so that readout starts from x_addr_end + 1 and ends at x_addr_start. figure 24 shows a sequence of 6 pixels being read out with r0x3040[14] = 0 and r0x3040[14] = 1. figure 24. effect of horizontal mirror on readout order g0[11:0] r0[11:0] g1[11:0] r1[11:0] g2[11:0] r2[11:0] r2[11:0] g2[11:0] r1[11:0] g1[11:0] r0[11:0] g3[11:0] line_valid horizontal_mirror = 0 horizontal_mirror = 1 d out [11:0] d out [11:0] vertical flip when the vert_flip bit (r0x3040[15]) is set in the read_mode register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. figure 30 shows a sequence of 6 rows being read out with r0x3040[15] = 0 and r0x3040[15] = 1. figure 25. effect of vertical flip on readout order row0[11:0] row1[11:0] row2[11:0] row3[11:0] row4[11:0] row5[11:0] row5[11:0] row4[11:0] row3[11:0] row2[11:0] frame_valid vertical_flip = 0 vertical_flip = 1 row1[11:0] d out [11:0] d out [11:0] row6[11:0] row2[11:0]
ar0331 www. onsemi.com 27 subsampling the ar0331 supports subsampling. subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. the following examples are configured to use either 2 x 2 or 3 x 3 subsampling. figure 26. horizontal binning in the ar0331 sensor isb isb isb isb isb isb horizontal binning is achieved either in the pixel readout or the digital readout. the sensor will sample the combined 2x or 3x adjacent pixels within the same color plane. figure 27. vertical row binning in the ar0331 sensor e ? e ? e ? e ? vertical row binning is applied in the pixel readout. row binning can be configured as 2x or 3x rows within the same color plane. pixel skipping can be configured up to 2x and 3x in both the x-direction and y-direction. skipping pixels in the x-direction will not reduce the row time. skipping pixels in the y-direction will reduce the number of rows from the sensor effectively reducing the frame time. skipping will introduce image artifacts from aliasing. refer to the ar0331 developer guide for details on configuring skipping, binning, and summing modes for color and monochrome operation.
ar0331 www. onsemi.com 28 sensor frame rate the time required to read out an image frame (t frame ) can be derived from the number of clocks required to output each image and the pixel clock. the frame-rate is the inverse of the frame period. fps 1 t frame (eq. 3) the number of clocks can be simplified further into the following parameters: ? the number of clocks required for each sensor row (line_length_pck) this parameter also determines the sensor row period when referenced to the sensor readout clock. (t row = line_length_pck x 1/clk_pix) ? the number of row periods per frame (frame_length_lines) ? an extra delay between frames used to achieve a specific output frame period (extra_delay) t frame 1 (clk_pix) [frame_length_lines line_length_pck extra_delay] (eq. 4) figure 28. frame period measured in clocks row period (t row ) line_length_pck will determine the number of clock periods per row and the row period (t row ) when combined with the sensor readout clock. line_length_pck includes both the active pixels and the horizontal blanking time per row. the sensor utilizes two readout paths, as seen in figure 21, allowing the sensor to output two pixels during each pixel clock. the minimum line_length_pck is defined as the maximum of the following three equations: adc readout limitation: line_length_pck 1100 (eq. 5) digital readout limitation: 1 3 x_addr_end?x_addr_start 1 (x_odd_inc 1) 0.5 (eq. 6) output interface limitations: 1 2 x_addr_end?x_addr_start 1 (x_odd_inc 1) 0.5 96 (eq. 7) row periods per frame frame_length_lines determines the number of row periods (t row ) per frame. this includes both the active and blanking rows. the minimum vertical blanking value is defined by the number of ob rows read per frame, two embedded data rows, and two blank rows. a minimum number of idle rows equal to the t2 integration time should be added in hdr mode to allow for changes in integration time by an auto exposure algorithm. for example, if the coarse integration time is 320 lines and the exposure ratio is 16x, then the minimum vertical blanking would be 8 + 2 + 2 + 20 = 32 rows. the minimum (default) number of idle rows is 4. minimum frame_length_lines y_addr_end?y_addr_start 1 (y_odd_inc 1) 2 min_vertical_blanking (eq. 8) the sensor is configured to output frame information in two embedded data rows by setting r0x3064[8] to 1 (default). if r0x3064[8] is set to 0, the sensor will instead output two blank rows. the data configured in the two embedded rows is defined in ?embedded data and statistics?.
ar0331 www. onsemi.com 29 table 16. minimum vertical blanking configuration r0x3180[7:4] ob rows min_vertical_blanking (note 1) 0x8 (default) 8 ob rows 8 ob + 8 = 16 0x4 4 ob rows 4 ob + 8 = 12 0x2 2 ob rows 2 ob + 8 = 10 1. min_vertical_blanking includes the default number (4) of idle rows. the locations of the ob rows, embedded rows, and blank rows within the frame readout are identified in figure 29: ?slave mode active state and vertical blanking,? . slave mode the slave mode feature of the ar0331 supports triggering the start of a frame readout from a vd signal that is supplied from an external asic. the slave mode signal allows for precise control of frame rate and register change updates. the vd signal is an edge triggered input to the trigger pin and must be at least 3 pixclk cycles wide. figure 29. slave mode active state and vertical blanking start of frame n end of frame n time start of frame n + 1 frame valid ob rows (2, 4, or 8 rows) embedded data row (2 rows) active data rows blank rows (2 rows) extra vertical blanking (frame_length_lines ? min_frame_length_lines) vd signal slave mode active state the period between the rising edge of the vd signal and the slave mode ready state is t frame + 16 clock extra delay (clocks) if the slave mode is disabled, the new frame will begin after the extra delay period is finished. the slave mode will react to the rising edge of the input vd signal if it is in an active state. when the vd signal is received, the sensor will begin the frame readout and the slave mode will remain inactive for the period of one frame time plus 16 clock periods (t frame + (16 / clk_pix)). after this period, the slave mode will re-enter the active state and will respond to the vd signal.
ar0331 www. onsemi.com 30 figure 30. slave mode example with equal integration and frame readout periods row 0 row n rising edge rising edge row readout programmed integration integration due to slave mode delay slave mode trigger rising edge of vd signal triggers the start of the frame readout. row reset (start of integration) frame valid vd signal rising edge the slave mode will become ?active? after the last row period. both the row reset and row read operations will wait until the rising edge of the vd signal. . row reset and read operations begin after the rising edge of the vd signal. active active inactive inactive note: the integration of the last row is started before the end of the programmed integration for the first row. the row shutter and read operations will stop when the slave mode becomes active and is waiting for the vd signal. the following should be considered when configuring the sensor to use the slave mode: 1. the frame period (t frame ) should be configured to be less than the period of the input vd signal. the sensor will disregard the input vd signal if it appears before the frame readout is finished. 2. if the sensor integration time is configured to be less than the frame period, then the sensor will not have reset all of the sensor rows before it begins waiting for the input vd signal. this error can be minimized by configuring the frame period to be as close as possible to the desired frame rate (period between vd signals). figure 31. slave mode example where the integration period is half of the frame readout period row 0 row n rising edge rising edge row readout programmed integration integration due to slave mode delay slave mode trigger row reset (start of integration) frame valid vd signal rising edge reset operation is held during slave mode ?active? state. row reset and read operations begin after the rising edge of the vd signal. 8.33 ms 8.33 ms active active inactive inactive note: the sensor read pointer will have paused at row 0 while the shutter pointer pauses at row n/2. the extra integration caused by the slave mode delay will only be seen by rows 0 to n/2. the example below is for a frame readout period of 16.6 ms while the integration time is configured to 8.33 ms.
ar0331 www. onsemi.com 31 when the slave mode becomes active, the sensor will pause both row read and row reset operations. (note: the row integration period is defined as the period from row reset to row read.) the frame-time should therefore be configured so that the slave mode ?wait period? is as short as possible. in the case where the sensor integration time is shorter than the frame time, the ?wait period? will only increase the integration of the rows that have been reset following the last vd pulse. the period between slave mode pulses must also be greater than the frame period. if the rising edge of the vd pulse arrives while the slave mode is inactive, the vd pulse will be ignored and will wait until the next vd pulse has arrived. to enter slave mode: 1. while in soft-standby, set r0x30ce[4] = 1 to enter slave mode 2. enable the input pins (trigger) by setting r0x301a[8] = 1 3. enable streaming by setting r0x301a[2] = 1 4. apply sync-pulses to the trigger input frame readout the sensor readout begins with vertical blanking rows followed by the active rows. the frame readout period can be defined by the number of row periods within a frame (frame_length_lines) and the row period ( line_length_pck/clk_pix ). the sensor will read the first vertical blanking row at the beginning of the frame period and the last active row at the end of the row period. figure 32. example of the sensor output of a 1928 x 1088 frame at 60 fps active rows vertical blanking time 1/60s end of frame readout end of frame readout start of vertical blanking start of frame start of active row end of line serial sync codes end of frame row reset row read row reset row read frame valid line valid 1/60s row reset row read row reset row read 1928 x 1088 1928 x 1088 hb (136 pixels/column) hb (136pixels/column) vb (37 rows) vb (37 rows) note: the frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. the sync codes represented in this diagram represent the hispi streaming ? sp protocol. figure 32 aligns the frame integration and readout operation to the sensor output. it also shows the sensor output using the hispi streaming-sp protocol. different sensor protocols will list different sync codes.
ar0331 www. onsemi.com 32 table 17. serial sync codes included with each protocol included with the ar0331 sensor interface/protocol start of vertical blanking row (sov) start of frame (sof) start of active line (sol) end of line (eol) end of frame (eof) parallel parallel interface uses frame valid (fv) and line valid (lv) outputs to denote start and end of line and frame. hispi streaming-s required unsupported required unsupported unsupported hispi streaming-sp required required required unsupported unsupported hispi packetized sp unsupported required required required required figure 33 illustrates how the sensor active readout time can be minimized while reducing the frame rate. 1125 vb rows were added to the output frame to reduce the 1928 x1088 frame rate from 60 fps to 30 fps without increasing the delay between the readout of the first and last active row. figure 33. example of the sensor output of a 1928 x 1088 frame at 30 fps active rows vertical blanking time 1/30 s end of frame readout end of frame readout start of vertical blanking start of frame start of active row end of line serial sync codes end of frame row reset row read row reset row read frame valid line valid 1/30 s row reset row read row reset row read vb (37 rows) h b (1236 p ix e ls ) 1928 x 1088 vb (37 rows) note: the frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. the sync codes represented in this diagram represent the hispi streaming ? sp protocol. h b (1236 p ix e ls ) 1928 x 1088
ar0331 www. onsemi.com 33 changing sensor modes register changes all register writes are delayed by one frame. a register that is written to during the readout of frame n will not be updated to the new value until the readout of frame n+2 . this includes writes to the sensor gain and integration registers. real-time context switching in the ar0331, the user may switch between two full register sets a and b by writing to a context switch change bit in r0x30b0[13]. when the context switch is configured to context a the sensor will reference the context a registers. if the context switch is changed from a to b during the readout of frame n , the sensor will then reference the context b coarse_integration_time registers in frame n+1 and all other context b registers at the beginning of reading frame n+2 . the sensor will show the same behavior when changing from context b to context a. table 18. list of configurable registers for context a and context b context a context b register description address register description address coarse_integration_time 0x3012 coarse_integration_time_cb 0x3016 line_length_pck 0x300c line_length_pck_cb 0x303e frame_length_lines 0x300a frame_length_lines_cb 0x30aa row_bin 0x3040[12] row_bin_cb 0x3040[10] col_bin 0x3040[13] col_bin_cb 0x3040[11] fine_gain 0x3060[3:0] fine_gain_cb 0x3060[11:8] coarse_gain 0x3060[5:4] coarse_gain_cb 0x3060[13:12] x_addr_start 0x3004 x_addr_start_cb 0x308a y_addr_start 0x3002 y_addr_start_cb 0x308c x_addr_end 0x3008 x_addr_end_cb 0x308e y_addr_end 0x3006 y_addr_end_cb 0x3090 y_odd_inc 0x30a6 y_odd_inc_cb 0x30a8 x_odd_inc 0x30a2 x_odd_inc_cb 0x30ae green1_gain 0x3056 green1_gain_cb 0x30bc blue_gain 0x3058 blue_gain_cb 0x30be red_gain 0x305a red_gain_cb 0x30c0 green2_gain 0x305c green2_gain_cb 0x30c2 global_gain 0x305e global_gain_cb 0x30c4 operation_mode_ctrl 0x3082 operation_mode_ctrl_cb 0x3084 bypass_pix_comb 0x318e[13:12] bypass_pix_comb_cb 0x318e[15:14]
ar0331 www. onsemi.com 34 figure 34. example of changing the sensor from context a to context b active rows vertical blanking time 1/60 s end of frame readout end of frame readout start of vertical blanking start of frame start of active row serial sync codes end of frame 1/60 s 1928x1088 frame n vb (37 rows) hb (136 pixels/column) vb (37 rows) hb (136 pixels/column) vb (37 rows) hb (76 pixels/column) ) write context a to b during readout of frame n integration time of context b mode implemented during readout of frame n+1 context b mode is implemented in frame n+2 1/30 s end of frame readout 1928x1088 frame n + 1 2048x1536 frame n + 2 combi mode to facilitate faster switching between linear and hdr modes, the ar0331 includes a combi mode feature. when enabled, combi mode loads a single (hdr) sequencer. when switching from hdr to linear modes, the sequencer remains the same, but only the t1 image is output. while not optimized for linear mode operation, it allows faster mode switching as a new sequencer load is not needed. combi mode is enabled by setting bit r0x30ba[8]. see the ar0331 developer guide for more information on combi mode. compression when the ar0331 is configured for linear mode operation, the sensor can optionally compress 12-bit data to 10-bit using a-law compression. the compression is applied after the data pedestal has been added to the data. see ?pedestals?. the a-law compression is disabled by default and can be enabled by setting r0x31d0 from ?0? to ?1?. table 19. a ? law compression table for 12 ? 10 bits input range input values compressed codeword 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 to 127 0 0 0 0 0 a b c d e f g 0 0 0 a b c d e f g 128 to 255 0 0 0 0 1 a b c d e f g 0 0 1 a b c d e f g 256 to 511 0 0 0 1 a b c d e f g x 0 1 0 a b c d e f g 512 to 1023 0 0 1 a b c d e f g x x 0 1 1 a b c d e f g 1024 to 2047 0 1 a b c d e f g h x x 1 0 a b c d e f g h 2048 to 4095 1 a b c d e f g h x x x 1 1 a b c d e f g h temperature sensor the ar0331 sensor has a built-in ptat-based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. the temperature sensor can be enabled by writing r0x30b4[0]=1 and r0x30b4[4]=1. after this, the temperature sensor output value can be read from r0x30b2[9:0]. the value read out from the temperature sensor register is an adc output value that needs to be converted downstream to a final temperature value in degrees celsius. since the ptat device characteristic response is quite linear in the temperature range of operation required, a simple linear function in the format of the equation below can be used to convert the adc output value to the final temperature in degrees celsius. temperature slope r0x30b2[9 : 0] t 0 (eq. 9) for this conversion, a minimum of two known points are needed to construct the line formula by identifying the slope and y-intercept ?t 0 ?. these calibration values can be read from registers r0x30c6 and r0x30c8, which correspond to
ar0331 www. onsemi.com 35 value read at 70 c and 55 c respectively. once read, the slope and y-intercept values can be calculated and used in equation 9. for more information on the temperature sensor registers, refer to the ar0331 register reference. embedded data and statistics the ar0331 has the capability to output image data and statistics embedded within the frame timing. there are two types of information embedded within the frame readout. ? embedded data: if enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. ? embedded statistics: if enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. figure 35. frame format with embedded data lines enabled image register data status & statistics data hblank vblank embedded data the embedded data contains the configuration of the image being displayed. this includes all register settings used to capture the current frame. the registers embedded in these rows are as follows: ? line 1: registers r0x3000 to r0x312f ? line 2: registers r0x3136 to r0x31bf, r0x31d0 to r0x31ff note: all undefined registers will have a value of 0. the format of the embedded register data transmission is defined per the embedded data section of the smia function specification. in parallel mode, since the pixel word depth is 12 bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where the register data will be broken up into 8 msb and 8 lsb. the alignment of the 8-bit data will be on the 8 msb bits of the 12-bit pixel word. for example, if a register value of 0x1234 is to be transmitted, it will be transmitted over two, 12-bit pixels as follows: 0x120, 0x340. embedded statistics the embedded statistics contain frame identifiers and histogram information of the image in the frame. this can be used by downstream auto-exposure algorithm blocks to make decisions about exposure adjustment. this histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 2 8 , 120 evenly spaced bins for values 2 8 to 2 12 , 60 evenly spaced bins for values 2 12 to 2 16 . in hdr with a 16x exposure ratio, this approximately corresponds to the t1 and t2 exposures respectively. the statistics found in line 2 are for backwards compatibility. it is recommended that auto exposure algorithms be developed using the histogram statistics on line 1. the first pixel of each line in the embedded statistics is a tag value of 0x0b0. this signifies that all subsequent statistics data is 10 bit data aligned to the msb of the 12-bit pixel. figure 36 summarizes how the embedded statistics transmission looks like. it should be noted that data, as shown in figure 36, is aligned to the msb of each word:
ar0331 www. onsemi.com 36 figure 36. format of embedded statistics output within a frame {2?b00,frame _countlsb} {2?b00,frame _idmsb} {2?b00,frame _idlsb} histogram bin0[9:0] histogram bin1[9:0] #words= 10?h1ec data_format_ code=8?h0b #words= 10?h00c data_format_ code=8?h0b mean [9:0] histbegin [19:10] histbegin [9:0] histend [19:10] histend [9:0] lowendmean [19:10] lowendmean [9:0] perc_lowend [19:10] perc_lowend [9:0] norm_abs_ dev[19:10] norm_abs_ dev[9:0] 8?h07 8?h07 8?h07 statsline1 statsline2 histogram bin0[19:10] histogram bin243 [19:0] histogram bin243 [9:0] histogram bin1 [19:0] mean [19:10] the statistics embedded in these rows are as follows: line 1: ? 0x0b0 ? identifier ? register 0x303a ? frame_count ? register 0x31d2 ? frame id ? histogram data ? histogram bins 0 ? 243 line 2: ? 0x0b0 (tag) ? mean ? histogram begin ? histogram end ? low end histogram mean ? percentage of pixels below low end mean ? normal absolute deviation test patterns the ar0331 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. with one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. test patterns are selected by test_pattern_mode register (r0x3070). only one of the test patterns can be enabled at a given point in time by setting the test_pattern_mode register according to table 20. when test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in test_pattern_green (r0x3074 and r0x3078) for green pixels, test_pattern_blue (r0x3076) for blue pixels, and test_pattern_red (r0x3072) for red pixels. table 20. test pattern modes test_pattern_mode test pattern output 0 no test pattern (normal operation) 1 solid color test pattern 2 100% vertical color bars test pattern 3 fade-to-gray vertical color bars test pattern 256 walking 1s test pattern (12-bit) solid color when the color field mode is selected, the value for each pixel is determined by its color. green pixels will receive the value in test_pattern_green, red pixels will receive the value in test_pattern_red, and blue pixels will receive the value in test_pattern_blue. vertical color bars when the vertical color bars mode is selected, a typical color bar pattern will be sent through the digital pipeline. walking 1s when the walking 1 s mode is selected, a walking 1 s pattern will be sent through the digital pipeline. the first value in each row is 1.
ar0331 www. onsemi.com 37 two-wire serial register interface the two-wire serial interface bus enables read/write access to control and status registers within the ar0331. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd_ io off-chip by a 1.5 k resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the two-wire serial interface specification allow the slave device to drive s clk low; the ar0331 uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is def ined as a low -to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/data direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the ar0331 are 0x20 (write address) and 0x21 (read address) in accordance with the specification. alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the s addr input. an alternate slave address can also be programmed through r0x31fc. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowledge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s internal register address is automatically incremented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
ar0331 www. onsemi.com 38 single read from random location this sequence (figure 37) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates the write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master terminates the read by generating a no-acknowledge bit followed by a stop condition. figure 37 shows how the internal register address maintained by the ar0331 is loaded and incremented as the sequence proceeds. figure 37. single read from random location previous reg address, n reg address, m m+1 s0 1 p a sr slave address reg address[15:8] reg address[7:0] slave address s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave a a a a read data single read from current location this sequence (figure 38) performs a read using the current value of the ar0331 internal register address. the master terminates the read by generating a no-acknowledge bit followed by a stop condition. the figure shows two independent read sequences. n+l n+l ? 1 n+2 n+1 previous reg address, n p a s 1 read data a slave address read data read data read data aaa figure 38. single read from current location sequential read, start from random location this sequence (figure 42) starts in the same way as the single write to random location (figure 41). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 39. sequential read, start from random location previous reg address, n reg address, m s0 slave address a a reg address[15:8] p a m+1 a a a 1 sr reg address[7:0] read data slave address m+l m+l ? 1 m+l ? 2 m+1 m+2 m+3 a read data a read data a read data read data
ar0331 www. onsemi.com 39 sequential read, start from current location this sequence (figure 40) starts in the same way as the single read from current location (figure 38). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 40. sequential read, start from current location n+l n+l ? 1 n+2 n+1 previous reg address, n p a s 1 read data a slave address read data read data read data aaa single write to random location this sequence (figure 41) begins with the master generating a start condition. the slave address/data direction byte signals a write and is followed by the high then low bytes of the register address that is to be written. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 41. single write to random location previous reg address, n reg address, m m+1 s0 slave address a reg address[15:8] a a a a reg address[7:0] write data p sequential write, start at random location this sequence (figure 42) starts in the same way as the single write to random location (figure 41). instead of generating a no ? acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 42. sequential write, start at random location previous reg address, n reg address, m m+1 s0 slave address a reg address[15:8] a a a reg address[7:0] m+l m+l ? 1 m+l ? 2 m+1 m+2 m+3 write data a a a p a write data write data a write data write data
ar0331 www. onsemi.com 40 spectral characteristics figure 43. quantum efficiency 0 5 10 15 20 25 30 35 40 45 50 350 450 550 650 750 wavelength (nm) quantum efficiency ( %) 850 950 1050 1150 g re e n r e d b l u e 55 60 65
ar0331 www. onsemi.com 41 electrical specifications unless otherwise stated, the following specifications apply under the following conditions: ? v dd = 1.8 v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8 v 0.3 v; ? v dd _slvs = 0.4 v ? 0.1/+0.2; t a = ? 30 c to +85 c; output load = 10 pf; ? frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 44 and table 21. figure 44. two-wire serial bus timing parameters s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 21. two ? wire serial bus characteristics ( f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v; t a = 25 c) parameter symbol standard mode fast mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition after this period, the first clock pulse is generated t hd;sta 4.0 ? 0.6 ? s low period of the sclk clock t low 4.7 ? 1.3 ? s high period of the sclk clock t high 4.0 ? 0.6 ? s set up time for a repeated start condition t su;sta 4.7 ? 0.6 ? s data hold time t hd;dat 0 (note 4) 3.45 (note 5) 0 (note 6) 0.9 (note 5) s data set-up time t su;dat 250 ? 100 (note 6) ? ns rise time of both s data and s clk signals t r ? 1000 20 + 0.1cb (note 7) 300 ns fall time of both s data and s clk signals t f ? 300 20 + 0.1cb (note 7) 300 ns set-up time for stop condition t su;sto 4.0 ? 0.6 ? s bus free time between a stop and start condition t buf 4.7 ? 1.3 ? s capacitive load for each bus line cb ? 400 ? 400 pf serial interface input pin capacitance cin_si ? 3.3 ? 3.3 pf s data max load capacitance cload_sd ? 30 ? 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1 v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk .
ar0331 www. onsemi.com 42 5. the maximum t hd;dat has only to be met if the device does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. i/o timing by default, the ar0331 launches pixel data, fv, and lv with the rising edge of pixclk. the expectation is that the user captures d out [11:0], fv, and lv using the falling edge of pixclk. see figure 45 below and table 22 for i/o timing (ac) characteristics. figure 45. i/o timing diagram data[11:0] frame_valid/ line_valid frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. pixclk extclk 90 % 10 % 90 % 10 % t pd t cp t pd pxl_0 pxl_1 pxl_2 pxl_n t pfh t plh t pfl t pll t extclk t r t f t rp t fp *pll disabled for t cp table 22. i/o timing characteristics symbol definition condition min typ max unit f extclk1 input clock frequency 6 ? 48 mhz t extclk1 input clock period 20.8 ? 166 ns t r input clock rise time ? 3 ? ns t f input clock fall time ? 3 ? ns t rp pixclk rise time ? 4 ? ns t fp pixclk fall time ? 4 ? ns clock duty cycle 40 50 60 % t (pix jitter) jitter on pixclk ? 1 ns t cp extclk to pixclk propagation delay nominal voltages, pll disabled ? 11.3 ? ns f pixclk pixclk frequency default, nominal voltages 6 74.25 mhz t pd pixclk to data valid default, nominal voltages ? 2.3 ? ns
ar0331 www. onsemi.com 43 table 22. i/o timing characteristics (continued) symbol unit max typ min condition definition t pfh pixclk to fv high default, nominal voltages ? 1.5 ? ns t plh pixclk to lv high default, nominal voltages ? 2.3 ? ns t pfl pixclk to fv low default, nominal voltages ? 1.5 ? ns tpll pixclk to lv low default, nominal voltages ? 2 ? ns c load output load capacitance ? <10 ? pf c in input pin capacitance ? 2.5 ? pf 1. i/o timing characteristics are measured under the following conditions: ? temperature is 25 c ambient ? 10 pf load dc electrical characteristics the dc electrical characteristics are shown in the tables below. table 23. dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd_ io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd_ pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage vdd_io*0.7 ? ? v v il input low voltage ? ? vdd_io*0.3 v i in input leakage current no pull-up resistor; v in = v dd_ io or d gnd 20 ? ? a v oh output high voltage vdd_io ? 0.3 ? ? v v ol output low voltage ? ? 0.4 v i oh output high current at specified v oh ? 22 ? ? ma i ol output low current at specified v ol ? ? 22 ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. caution: stresses greater than those listed in table 14 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied
ar0331 www. onsemi.com 44 table 24. absolute maximum ratings symbol definition min max unit v dd _max core digital voltage ?0.3 2.4 v v dd _io_max i/o digital voltage ?0.3 4 v v aa _max analog voltage ?0.3 4 v v aa _pix pixel supply voltage ?0.3 4 v v dd _pll pll supply voltage ?0.3 4 v vdd_slvs_max hispi i/o digital voltage ?0.3 2.4 v t st storage temperature ?40 85 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. table 25. operating current consumption in parallel output and linear mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 20 fps i dd 1 ? 122 137 ma i/o digital operating current streaming, 2048x1536 20 fps i dd _io ? 25 30 ma analog operating current streaming, 2048x1536 20 fps i aa ? 32 38 ma pixel supply current streaming, 2048x1536 20 fps i aa _pix ? 7 12 ma pll supply current streaming, 2048x1536 20 fps i dd _pll ? 8 12 ma digital operating current streaming, 1080p30 i dd 1 ? 122 137 ma i/o digital operating current streaming, 1080p30 i dd _io ? 25 30 ma analog operating current streaming, 1080p30 i aa ? 35 40 ma pixel supply current streaming, 1080p30 i aa _pix ? 7 12 ma pll supply current streaming, 1080p30 i dd _pll ? 8 12 ma 1. operating currents are measured at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v v dd = v dd_ io = 1.8 v pll enabled and pixclk = 74.25 mhz t a = 25 c table 26. operating current consumption in parallel output and hdr mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 20 fps i dd ? 156 173 ma i/o digital operating current streaming, 2048x1536 20 fps i dd _io ? 30 35 ma analog operating current streaming, 2048x1536 20 fps i aa ? 50 65 ma pixel supply current streaming, 2048x1536 20 fps i aa _pix ? 9 14 ma pll supply current streaming, 2048x1536 20 fps i dd _pll ? 8 12 ma digital operating current streaming, 1080p30 i dd ? 161 184 ma i/o digital operating current streaming, 1080p30 i dd _io ? 30 35 ma analog operating current streaming, 1080p30 i aa ? 54 70 ma pixel supply current streaming, 1080p30 i aa _pix ? 9 14 ma pll supply current streaming, 1080p30 i dd _pll ? 8 12 ma 1. operating currents are measured at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v v dd = v dd _io = 1.8 v pll enabled and pixclk = 74.25 mhz pll enabled and pixclk = 74.25 mhz t a = 25 c
ar0331 www. onsemi.com 45 table 27. operating current in hispi (hivcm) output and linear mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 30fps i dd ? 252 278 ma analog operating current streaming, 2048x1536 30fps i aa ? 27 35 ma pixel supply current streaming, 2048x1536 30fps i aa _pix ? 5 10 ma pll supply current streaming, 2048x1536 30fps i dd _pll ? 8 12 ma slvs supply current streaming, 2048x1536 30fps i dd_ slvs ? 22 26 ma digital operating current streaming, 1080p60 i dd ? 276 302 ma analog operating current streaming, 1080p60 i aa ? 37 45 ma pixel supply current streaming, 1080p60 i aa _pix ? 7 12 ma pll supply current streaming, 1080p60 i dd _pll ? 8 12 ma slvs supply current streaming, 1080p60 i dd_ slvs ? 22 26 ma 1. operating currents are measured at the following conditions: v aa = v aa _pix = v dd _pll=2.8 v v dd = v dd _io= 1.8 v v dd _slvs = 1.8 v pll enabled and pixclk=74.25 mhz t a = 25 c table 28. operating current in hispi (hivcm) output and hdr mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 30fps i dd ? 317 358 ma analog operating current streaming, 2048x1536 30fps i aa ? 45 55 ma pixel supply current streaming, 2048x1536 30fps i aa _pix ? 8 13 ma pll supply current streaming, 2048x1536 30fps i dd _pll ? 8 12 ma slvs supply current streaming, 2048x1536 30fps i dd_ slvs ? 22 26 ma digital operating current streaming, 1080p60 i dd ? 323 358 ma analog operating current streaming, 1080p60 i aa ? 55 70 ma pixel supply current streaming, 1080p60 i aa _pix ? 9 14 ma pll supply current streaming, 1080p60 i dd _pll ? 8 12 ma slvs supply current streaming, 1080p60 i dd_ slvs ? 24 28 ma 1. operating currents are measured at the following conditions: v aa = v aa _pix = v dd _pll=2.8 v v dd = v dd _io= 1.8 v v dd _slvs = 1.8 v pll enabled and pixclk = 74.25 mhz t a = 25 c table 29. operating current in hispi (slvs) output and linear mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 30fps i dd ? 252 278 ma analog operating current streaming, 2048x1536 30fps i aa ? 27 35 ma pixel supply current streaming, 2048x1536 30fps i aa _pix ? 5 10 ma pll supply current streaming, 2048x1536 30fps i dd _pll ? 8 12 ma slvs supply current streaming, 2048x1536 30fps i dd_ slvs ? 9 13 ma digital operating current streaming, 1080p60 i dd ? 276 302 ma analog operating current streaming, 1080p60 i aa ? 37 45 ma pixel supply current streaming, 1080p60 i aa _pix ? 7 12 ma
ar0331 www. onsemi.com 46 table 29. operating current in hispi (slvs) output and linear mode (continued) definition unit max typ min symbol condition pll supply current streaming, 1080p60 i dd _pll ? 8 12 ma slvs supply current streaming, 1080p60 i dd_ slvs ? 9 13 ma 1. operating currents are measured at the following conditions: v aa = v aa _pix= v dd _pll=2.8 v v dd =v dd _io= 1.8 v v dd _slvs = 0.4 v pll enabled and pixclk=74.25 mhz t a = 25 c table 30. operating current in hispi (slvs) output and hdr mode definition condition symbol min typ max unit digital operating current streaming, 2048x1536 30fps i dd ? 317 358 ma analog operating current streaming, 2048x1536 30fps i aa ? 45 55 ma pixel supply current streaming, 2048x1536 30fps i aa _pix ? 8 13 ma pll supply current streaming, 2048x1536 30fps i dd _pll ? 8 12 ma slvs supply current streaming, 2048x1536 30fps i dd_ slvs ? 9 13 ma digital operating current streaming, 1080p60 i dd ? 323 358 ma analog operating current streaming, 1080p60 i aa ? 55 70 ma pixel supply current streaming, 1080p60 i aa _pix ? 9 14 ma pll supply current streaming, 1080p60 i dd _pll ? 8 12 ma slvs supply current streaming, 1080p60 i dd_ slvs ? 9 13 ma 1. operating currents are measured at the following conditions: vaa=vaa_pix= vdd_pll=2.8 v vdd = vdd_io= 1.8 v vdd_slvs = 0.4 v pll enabled and pixclk=74.25 mhz t a = 25 c hispi electrical specifications the on semiconductor ar0331 sensor supports both slvs and hivcm hispi modes. please refer to the high-speed serial pixel (hispi) interface physical layer specification v2.00.00 for electrical definitions, specifications, and timing information. the v dd _slvs supply in this datasheet corresponds to v dd _tx in the hispi physical layer specification. similarly, v dd is equivalent to v dd _hispi as referenced in the specification. the dll as implemented on ar0331 is limited in the number of available delay steps and differs from the hispi specification as described in this section. table 31. channel skew (measurement conditions: vdd_hispi = 1.8 v; vdd_hispi_tx = 0.8 v; data rate = 480 mbps; dll set to 0) data lane skew in reference to clock tchskew1phy ? 150 ps table 32. clock dll steps (measurement conditions: vdd_hispi = 1.8 v; vdd_hispi_tx = 0.8 v; data dll set to 0) clock dll step 1 2 3 4 5 6 delay at 660 mbps 0.25 0.375 0.5 0.625 0.75 ui eye_opening at 660 mbps 0.85 0.78 0.71 0.71 0.69 ui 1. the clock dll steps 6 and 7 are not recommended by on semiconductor for the ar0331.
ar0331 www. onsemi.com 47 table 33. data dll steps (measurement conditions: vdd_hispi = 1.8 v;vdd_hispi_tx = 0.8 v; data dll set to 0) clock dll step 1 2 4 6 step delay at 660 mbps 0.25 0.375 0.625 0.875 ui eye opening at 660 mbps 0.79 0.84 0.71 0.61 ui eye opening at 360 mhz 0.85 0.83 0.82 0.77 ui 1. the data dll steps 3, 5, and 7 are not recommended by on semiconductor for the ar0331. power-on reset and standby timing power-up sequence the recommended power-up sequence for the ar0331 is shown in figure 46. the available power supplies (v dd_ io, v dd , v dd_ slvs , v dd _pll, v aa , v aa_ pix) must have the separation specified below. 1. turn on v dd_ pll power supply 2. after 100 s, turn on v aa and v aa_ pix power supply 3. after 100 s, turn on v dd _io power supply 4. after 100 s, turn on vdd power supply 5. after 100 s, turn on vdd_slvs power supply 6. after the last power supply is stable, enable extclk 7. assert reset_bar for at least 1 ms. the parallel interface will be tri-stated during this time 8. wait 150000 extclks (for internal initialization into software standby 9. configure pll, output, and image settings to desired values 10. wait 1ms for the pll to lock 11. set streaming mode (r0x301a[2] = 1) figure 46. power up v dd _pll (2.8) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) extclk reset_bar t0 t1 t2 t3 tx t4 t5 t6 hard reset internal initialization software standby pll lock streaming
ar0331 www. onsemi.com 48 table 34. power up sequence definition symbol minimum typical maximum unit v dd _pll to v aa /v aa _pix (note 3) t0 0 100 ? s v aa /v aa _pix to v dd _io t1 0 100 ? s v dd _io to v dd t2 0 100 ? s v dd to v dd _slvs t3 0 100 ? s xtal settle time tx ? 30 (note 1) ? ms hard reset t4 1 (note 2) ? ? ms internal initialization t5 150000 ? ? extclks pll lock time t6 1 ? ? ms 1. xtal settling time is component-dependent, usually taking about 10 ? 100 ms. 2. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc time must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. power-down sequence the recommended power-down sequence for the ar0331 is shown in figure 47. the available power supplies (v dd_ io, v dd , v dd_ slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depending on configuration, has ended 3. turn off v dd _slvs 4. turn off v dd 5. turn off v dd _io 6. turn off v aa /v aa _pix 7. turn off v dd _pll figure 47. power down v dd _io (1.8/2.8) t4 t 0 t1 t3 extclk v dd _slvs (0.4) v dd (1.8) v aa _pix (2.8) v dd _pll (2.8) power down until next power up cycle t2 v aa
ar0331 www. onsemi.com 49 table 35. power down sequence definition symbol minimum typical maximum unit v dd _slvs to v dd t0 0 ? ? s v dd to v dd _io t1 0 ? ? s v dd _io to v aa /v aa _pix t2 0 ? ? s v aa /v aa _pix to v dd _pll t3 0 ? ? s pwrdn until next pwrup time t4 100 ? ? ms 1. t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
ar0331 www. onsemi.com 50 ilcc48 10 x 10 case 847ag issue o
ar0331 www. onsemi.com 51 ibga63 9.5 x 9.5 case 503am issue o
ar0331 www. onsemi.com 52 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ar0331/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ? a ? pix is a trademark of semiconductor components industries, llc (scillc) or its subsidiaries in the united states and/or other c ountries.

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